MIPS processor construction is a kind of manycore processors thought of as the normal model architecture of processor in the traditional computer class architecture particularly for undergraduate learners (Park et al., 2013). MIPS processors can be pipelined or non pipelined (unpipelined types). This paper compares pipelined versus unpipelined MIPS processors in terms of the insertion of forwarding and branch prediction hardware with consideration of FPGA platform. The comparison is also done in terms of cost/area and frequency of processor. The final comparison is also done based on the CPU time of the two types of MIPS processors. It was found that the two types of processors have different performance at different situations. The unpipelined MIPS processor has the shortest CPU time because of its direct mapping of cache controller to the CPU. The pipelined MIPS processor can perform better when several instructions are to be executed at the same time and when the maximum depth of pipeline is used to enhance the frequency of the processor.
Introduction to MIPS processor on an FPGA
The design of MIPS processor is normally regarded as the typical structural design of the processor model in the context of the usual class of computer architecture for undergraduate students. The design are developed in such a way that they make use of parallel applications that are easy enough to permit the students to appreciate the whole design of manycore processor and to be able to learn its fundamental parts together with the fundamental structural design of communication ( Park et al., 2013).
The programmable FPGA devices can also be used in the processor design since it can allow the students to make the real working processor chip by means of downloading the plans to the FPGA. This is very different from simply conducting a test based on the simulation of the software. The device for FPGA also offers a fast test cycle and amendment ability that is simpler. As a result, the learners can be able to practice every process of real processor design through working on plan, completion, testing and even debugging processors by means of commercial FPGA improvement boards. The plan can also be used to implement FPGA with a small power pipelined processor especially for the 32-bit model of RISC core. The components of the pipelined MIPS architecture consist of control logic, register blocks, and memory, low power unit and datapath. The registers, addresses, layouts and instruction sets among others defines the architecture of the processor for MIPS. On the other hand, the way in which various processors employ the architecture in the construction of the model defines the implementation of the hardware part of it (Park et al., 2013, Bhosle & Moorthy, 2012).
Unpipelined MIPS processor
Unpipelined MIPs processor involves the straight mapping of the controller for cache for microprocessor without the pipeline stages that are interlocked. This comprises of the use of extremely high rate hardware narrative language plan. In this case, both the instruction for cache together with data cache is detached from each other and is situated within the central part of central processing unit. After concluding with the construction of cache for the controller, it is later joined with the processor for the pipelined MIPS and used in the execution of the program. The fusion of the processor design can be accomplished using 13.4 version of design suit for the Xilinx ISE. The simulation is then carried out by means of a simulator called Xilinx Isim (Mahmood & Omran, 2013). In addition, it should be noted that the core of unpipelined MIPS consists of simple and competent structural design (El Kateeb, 2013).
Pipelining refers to the method that permits the execution of many instructions simultaneously. In this case, many sections of the instructions which are successive in nature are performed at the same time. Pipelining is extensively employed in the architectural design of microprocessor with an aim of enhancing the processor performance as well as to enhance the use of resources for hardware. As mentioned earlier in the introduction, the components of the pipelined MIPS structural design comprises of control logic, register blocks and memory, low power unit and datapath (Han, He & Li, 2012). The core advancement of pipelined MIPS can also be employed for the pending generation network of sensor motes in order to sustain enhanced performance in processing, isolated design alterations, and mixed wireless sensor networks. The design of pipelined MIPS involves decomposing the IF instruction fetch, decoding instruction, instruction execution, memory input, and output and write back respectively (Bhor, Priya & Malathi, 2014).
Pipelined MIPS processor by inserting Forwarding hardware
The pipelined MIPS processor comprises of general parts in the design of the pipeline. They include registers for the pipeline, controller, the hazard discovery parts as well as logics for hazard reduction. The logics for hazard reduction include the forwarding approached like execution to execution forwarding and memory to execution forwarding. Apart from that, there is also a module for memory to memory forwarding that can be put into action in order to remove the possible hazard within the stage of memory (Han, He & Li, 2012). Both the dynamic and elaborate static forwarding can be very sophisticated. On the other hand, the use of a controlled or constrained forwarding method can be simpler and can bring about considerable general performance enhancement. Instead of adding the path of forwarding from all stages after the stage of decode back to the stage input of execution, one or a single path can be taken into an account. The forwarding process can also be used to indicate how the consecutive program instructions can begin earlier in the pipeline. The insertion of forwarding hardware can reduce the number of NOPs needed to resolve the successive instruction dependencies. The use of simple data forwarding thus reduces the instruction counts by 4 to 30 percent for the case of fixed or constant path of forwarding (Cheah, Fahmy & Kapre, 2014).
Data hazard takes place when the outcome of the previous instruction is required within the pipeline prior to its availability or accessibility. The forwarding of register with pipeline interlock are used as the appropriate methods for evading corruption of data and to control the performance penalty that comes as a result of data hazards within the processors that are pipelined (Bernardi et al., 2013).
Pipelined MIPS processor by inserting Forwarding and Branch Prediction hardware
As mentioned above, the insertion of hardware for forwarding helps in reducing the number of NOPs needed to resolve the consecutive instruction dependencies, that is, reducing the number of instruction counts. The inclusion of branch hardware will help in the prediction of whether the branch ought to be taken or not. The outcome from the branch target buffer and the branch predictor direction is utilized in the determination of the branch direction. The inclusion of the branch hardware predictor is also used to avoid misprediction. The misprediction price or penalty for the branch is two cycles given that the instruction for the branch is succeeded by the delay branch slot of the instruction of the branch according to MIPS. The cache instruction is realized for access in two cycles by means of way prediction. The first clock cycle that is predicted by way predictor with a group of related cache is normally indexed. In the second cycle, the tag comparison is conducted to find out the data miss or data hit. Considering misprediction, the pipeline will be slowed down or hindered as the remaining ways of instruction cache is accessed (Rajendra, 2015).
Comparing the cost (area) and frequency of these Processors with each other
The cost (area) in this case is proportional to frequency. This is because the soft processors of FPGA which attains high frequency at a time when it is planned or constructed about some particular abilities of mixed resources within the platform of present or new FPGA whose performance is realized at high cost of using deep pipelines. This can in turn bring about a larger number of cycles that are idle during program execution by means of long chains of dependency within the sequence of instruction. This also implies that the architecture of the FPGA has to be considered when trying to take advantage of performance in the processor design. The use of low frequency, on the other hand, can fail to give enhanced performance. In this case, the smallest depth of pipeline required is one such that as the number of stages in the pipeline goes up, the frequency of the clock also goes up. The multiple pipeline stages can thus be enabled to get higher depth hence getting optimum frequency (Cheah, Fahmy & Kapre, 2014).
Comparing the CPU-Time of these Processors
The fact that unpipelined processor employs the controller with direct-mapped cache with no interlocked stages of pipeline makes it faster in terms of execution speed. Unpipelined processors also make use of very high speed integrated circuit hardware. This makes it have short execution time (short CPU time/ cycle) as compared to pipelined processors. However, the use of deep pipeline (maximum depth of pipeline) enhances the performance of the pipelined processors in terms of CPU time and frequency.
This paper is concerned with comparing pipeline versus unpipelined MIPS processors. The two types of processors are found to have good performance at different circumstances. Pipelined MIPS processors can perform better when the depth of the pipeline is increased since this also increases the frequency of the processor. The pipelined processor also performs better in terms of executing two or more instructions simultaneously as opposed to unpipelined processors. Nevertheless, the unpipelined MIPS processors also perform faster in terms of CPU time since it has a direct mapping of the controller cache to the CPU. The cache instructions together with the cache for data are detached are placed within the central part of the CPU. Therefore, the short CPU time used for the execution is due to the direct execution of instructions that takes place without any mapping.
Bernardi, P., Cantoro, R., Ciganda, L., Du, B., Sanchez, E., Reorda, M. S., … & Ballan, O. (2013, December). On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors. In Microprocessor Test and Verification (MTV), 2013 14th International Workshop on (pp. 52-57). IEEE.
Bhor, P. B., Priya, R. A., & Malathi, P. (2014). Customized Processor Design and its Run Time Configuration.
Bhosle, P., & Moorthy, H. K. (2012). FPGA Implementation of Low Power Pipelined 32-bit RISC Processor. Proceedings of International Journal of Innovative Technology and Exploring Engineering (IJITEE), ISSN, 2278-3075.
Cheah, H. Y., Fahmy, S. A., & Kapre, N. (2014). Analysis and optimization of a deeply pipelined FPGA soft processor. In Proceedings of the International Conference on Field Programmable Technology (FPT) (pp. 235-238).
El Kateeb, A. (2013). Mote Design Supported with Remote Hardware Modifications Capability for Wireless Sensor Network applications. International Journal of Advanced Smart Sensor Network Systems (IJASSN), 3(3).
Han, S., He, X., & Li, C. (2012). An Implementation of 32-bit Pipelined MIPS Processor with Multiplication-and-Accumulation (MAC) Support.
Mahmood, H. S., & Omran, S. S. (2013, December). Pipelined MIPS processor with cache controller using VHDL implementation for educational purposes. In Electrical, Communication, Computer, Power, and Control Engineering (ICECCPCE), 2013 International Conference on (pp. 82-87). IEEE.
Park, H., Ko, Y. W., So, J., & Lee, J. G. (2013). Manycore Processor Education Platform with FPGA for Undergraduate Level Computer Architecture Class.
RAJENDRA, K. M. (2015). Implementation and Verification of a 7-Stage Pipeline Processor.
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